1. Field of the Invention
The present invention relates to implementing a cryptography engine. More specifically, the present invention relates to methods and apparatus for handling interrupts from multiple processing engines.
2. Description of Related Art
Conventional software and hardware designs for implementing various cryptography engines often use a single processing engine. In one example, a single processor core is used to handle Internet Key Exchange (IKE) data. IKE and other key exchange algorithms are described in Applied Cryptography, Bruce Schneier, John Wiley & Sons, Inc. (ISBN 0471128457), incorporated by reference in its entirety for all purposes.
Typical implementations pass one block of data at a time to a processing engine. Some of these data blocks are associated with interrupt enable indicators. The interrupt enable indicator instructs the processing engine to generate an interrupt upon completion of processing of the data block. When an interrupt is generated, a host such as an external processor reads processed data blocks up through the data block associated with the generated interrupt. However, the sequential processing technique does not work well when multiple processing records are used. When multiple processing engines are used, data blocks may be processed out of order and the lack of sequence may cause a host such as an external processor to read incorrect data or stall because data blocks were processed out of an expected order.
It is therefore desirable to provide methods and apparatus for improving the handling of interrupts in the implementation of a cryptography engine with respect to some or all of the performance limitations noted above.